diff --git a/README.md b/README.md index 6e293a4b70bc862bac822a4c15e70dea12abc760..92929644d4f60f7f5e5699e63cda9924c3bbe43f 100644 --- a/README.md +++ b/README.md @@ -1,52 +1,52 @@ -# eda_qt - -### -介绍 -eda软件开发 - -## - 开发需求 -### ------------001------------ -点击“新建模块”按钮后，弹出一对话框，如： -![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/232300_bb1cd7c7_8607408.png "QQ截图20210123232228.png") - -用户可输入：模块名称、input端口数量、output端口数量、inout端口数量 -点击ok后，将出现一“矩形图”，代表着该模块 -![这是我们软件里用的矩形](https://images.gitee.com/uploads/images/2021/0123/232810_4125e7a6_8607408.png "矩形.png") -上图是我们要开发的软件里用的矩形图 -这是我们仿照的软件里的截图，模块名为123，input、output、inout都为1 -![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/232955_c341839e_8607408.png "QQ截图20210123232905.png") -点击某一端口时，应做到可以修改端口的属性，包括：![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233219_b40e4d51_8607408.png "QQ截图20210123233154.png") -|端口名：要在矩形图上体现 -|输入输出类型：可以在input、output、inout中选![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233346_328b5e77_8607408.png "QQ截图20210123233330.png") -|数据类型：可以在wire、reg中选![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233408_06262ce9_8607408.png "QQ截图20210123233336.png") -|数据长度：可设置正整数值 -|颜色：此功能目前可先不做。。 -### ------------002------------ -双击模块矩形，可进入用户代码编辑界面 -此时用户只需要输入算法代码 如：assign c = a & b; -其他代码由软件自动生成。 -![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234049_deade8af_8607408.png "QQ截图20210123234037.png") -其中第一段的格式为module xxx[*](端口名); 如用户在最开始的对话框中填写模块名为123，且整个模块中所有的端口为a、b、c三个时 -软件将会生成module 123[*](a,b,c); - **第二段** 代码为：input/output/inout 端口名；例如用户设置a为input,b为output,c为inout。则代码为 -input a; output b; inout c; - **第三段** 代码为：端口数据类型 端口名；例如用户定义a端口为wire型，b、c端口为reg型，则： -wire a; reg b; reg c; -第四段代码为之前用户输入的算法代码 -最后是固定句式：endmodule 相当于这个模块结束了 -另外要注意：当端口的数据长度定义为i（正整数）时，相应的在上述 **第二段、第三段** 代码中要有所改变，在端口名前加[i-1:0] -例如：![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234717_374091e7_8607408.png "QQ截图20210123234621.png")用户定义了p0为3位 -![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234922_d18c6d0d_8607408.png "QQ截图20210123234626.png") ![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234930_6490091b_8607408.png "QQ截图20210123234630.png") -则p0前面加[2:0] -### ------------003------------ -应有“保存模块”和“生成代码”两个按钮。其中： -保存模块：做到将此次用户新建的模块里的所有内容打包保存 下次用户双击时可以直接在软件里打开 -生成代码：将软件生成的代码 让用户选择位置保存。保存为 **verilog目录** 目录下应有 **此模块及其内部子模块** 所有的verilog代码文件 **扩展名为.v** - - - - - - - - - +# eda_qt + +### -介绍 +eda软件开发 + +## - 开发需求 +### ------------001------------ +点击“新建模块”按钮后，弹出一对话框，如： +![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/232300_bb1cd7c7_8607408.png "QQ截图20210123232228.png") + +用户可输入：模块名称、input端口数量、output端口数量、inout端口数量 +点击ok后，将出现一“矩形图”，代表着该模块 +![这是我们软件里用的矩形](https://images.gitee.com/uploads/images/2021/0123/232810_4125e7a6_8607408.png "矩形.png") +上图是我们要开发的软件里用的矩形图 +这是我们仿照的软件里的截图，模块名为123，input、output、inout都为1 +![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/232955_c341839e_8607408.png "QQ截图20210123232905.png") +点击某一端口时，应做到可以修改端口的属性，包括：![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233219_b40e4d51_8607408.png "QQ截图20210123233154.png") +|端口名：要在矩形图上体现 +|输入输出类型：可以在input、output、inout中选![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233346_328b5e77_8607408.png "QQ截图20210123233330.png") +|数据类型：可以在wire、reg中选![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/233408_06262ce9_8607408.png "QQ截图20210123233336.png") +|数据长度：可设置正整数值 +|颜色：此功能目前可先不做。。 +### ------------002------------ +双击模块矩形，可进入用户代码编辑界面 +此时用户只需要输入算法代码 如：assign c = a & b; +其他代码由软件自动生成。 +![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234049_deade8af_8607408.png "QQ截图20210123234037.png") +其中第一段的格式为module xxx[*](端口名); 如用户在最开始的对话框中填写模块名为123，且整个模块中所有的端口为a、b、c三个时 +软件将会生成module 123[*](a,b,c); + **第二段** 代码为：input/output/inout 端口名；例如用户设置a为input,b为output,c为inout。则代码为 +input a; output b; inout c; + **第三段** 代码为：端口数据类型 端口名；例如用户定义a端口为wire型，b、c端口为reg型，则： +wire a; reg b; reg c; +第四段代码为之前用户输入的算法代码 +最后是固定句式：endmodule 相当于这个模块结束了 +另外要注意：当端口的数据长度定义为i（正整数）时，相应的在上述 **第二段、第三段** 代码中要有所改变，在端口名前加[i-1:0] +例如：![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234717_374091e7_8607408.png "QQ截图20210123234621.png")用户定义了p0为3位 +![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234922_d18c6d0d_8607408.png "QQ截图20210123234626.png") ![输入图片说明](https://images.gitee.com/uploads/images/2021/0123/234930_6490091b_8607408.png "QQ截图20210123234630.png") +则p0前面加[2:0] +### ------------003------------ +应有“保存模块”和“生成代码”两个按钮。其中： +保存模块：做到将此次用户新建的模块里的所有内容打包保存 下次用户双击时可以直接在软件里打开 +生成代码：将软件生成的代码 让用户选择位置保存。保存为 **verilog目录** 目录下应有 **此模块及其内部子模块** 所有的verilog代码文件 **扩展名为.v** + + + + + + + + + diff --git a/src/eda_qt 1-24 2_06/eda_qt.pro.user b/src/eda_qt 1-24 2_06/eda_qt.pro.user index 3b57cffa115a7f8849962cfcfc88fd3742b2295e..5a3c13019379388821a0b4352ac7d90e84b11ceb 100644 --- a/src/eda_qt 1-24 2_06/eda_qt.pro.user +++ b/src/eda_qt 1-24 2_06/eda_qt.pro.user @@ -1,328 +1,328 @@ - - - - - - EnvironmentId - {d7319875-1e1d-4456-a97d-d87e35d07a5e} - - - ProjectExplorer.Project.ActiveTarget - 0 - - - ProjectExplorer.Project.EditorSettings - - true - false - true - - Cpp - - CppGlobal - - - - QmlJS - - QmlJSGlobal - - - 2 - UTF-8 - false - 4 - false - 80 - true - true - 1 - true - false - 0 - true - true - 0 - 8 - true - 1 - true - true - true - false - - - - ProjectExplorer.Project.PluginSettings - - - -fno-delayed-template-parsing - - true - - - - ProjectExplorer.Project.Target.0 - - Desktop Qt 5.12.1 MinGW 64-bit - Desktop Qt 5.12.1 MinGW 64-bit - qt.qt5.5121.win64_mingw73_kit - 0 - 0 - 0 - - F:/eda_dev/eda_qt/src/build-eda_qt-Desktop_Qt_5_12_1_MinGW_64_bit-Debug - - - true - qmake - - QtProjectManager.QMakeBuildStep - true - - false - false - false - - - true - Make - - Qt4ProjectManager.MakeStep - - false - - - false - - 2 - Build - - ProjectExplorer.BuildSteps.Build - - - - true - Make - - Qt4ProjectManager.MakeStep - - true - clean - - false - - 1 - Clean - - ProjectExplorer.BuildSteps.Clean - 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